1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a circuit for evaluating noise characteristic at the time of data output.
2. Description of the Background Art
FIG. 11 shows circuit configuration of output buffers 11, 13 and 15 of a conventional semiconductor memory device, and FIG. 12 shows a concept of a pattern layout of the output buffers.
As shown in FIG. 11, the output buffer is activated when an output control signal .phi. activated and at a high (H) level is input to NAND circuits 4 and 6.
In a semiconductor memory device having a plurality of input/output terminals 2 such as shown in FIG. 12, all output buffers are activated in normal operation, and data is output from every input/output terminal 2.
Here, N channel MOS transistors TN1 included in respective output buffers 11, 13 and 15 are connected together to one V.sub.CC line 1 as shown in FIG. 12, and therefore in a so-called multi-bit product having a large number of input/output terminals 2, there is a problem of considerable noise generated at the power supply voltage V.sub.CC at the time of data output. Therefore, it is necessary to minimize the influence of noise. In that case, what input/output terminal is susceptible to noise generation at the time of data output must be inspected. In the conventional semiconductor memory device, however, there is not any circuit provided for inspecting output terminal dependency of noise at the time of data output.